> ## Documentation Index
> Fetch the complete documentation index at: https://docs.oryx.mechatronstudio.com/llms.txt
> Use this file to discover all available pages before exploring further.

# I2C

> Two channels per bus —SDA and SCL— and several buses at once.

I2C is the only one of the four that **reads several channels together**: it
needs two lines, and returns a reading for each.

## Buses

You build the buses in the protocol window: each one with **which channel is
SDA** and **which is SCL**. You can add and remove them.

<Note>
  Each bus needs **two free channels**: one for SDA and one for SCL. With no buses
  set up, the notice asks for one: *"No bus yet. Add one and pick which channel is
  SDA and which is SCL."*
</Note>

If you never touch them, the editor sets them up on its own: by the channel
names, or with the first two.

## How it is read

> SDA is the data and SCL the clock. Every rising edge of SCL reads one bit;
> with SCL high, SDA falling is **START** and SDA rising is **STOP**.

## Transfer stretches

| Stretch             | What it is                                       |
| ------------------- | ------------------------------------------------ |
| **START**           | SDA falls while SCL is high: a transfer begins   |
| **Repeated START**  | A new address without releasing the bus          |
| **STOP**            | SDA rises while SCL is high: the bus is released |
| **Address**         | 7 bits, the slave being addressed                |
| **10-bit address**  | Starts with `11110`                              |
| **R**               | The master reads from the slave                  |
| **W**               | The master writes to the slave                   |
| **ACK**             | The receiver pulls SDA low: received correctly   |
| **NACK**            | SDA stayed high: no acknowledge                  |
| **Data byte**       | The payload                                      |
| **Incomplete byte** | Cut before its 9 bits                            |

## Errors it detects

| Label                  | What happened                                                      |
| ---------------------- | ------------------------------------------------------------------ |
| **No answer**          | Nobody answered the address: the acknowledge stayed NACK           |
| **Data NACK**          | The slave rejected a byte with a NACK                              |
| **Read after NACK**    | The master kept reading after a NACK                               |
| **Missing final NACK** | The last byte read must end with a NACK before the STOP            |
| **Incomplete byte**    | A STOP or START cut a byte before its 9 bits                       |
| **No STOP**            | The drawing ends without a STOP: the bus stays busy                |
| **No START**           | There are clock pulses while the bus is free: the START is missing |

## The summary

Each transfer is summed up with the address, the direction and the size:

* `0x3C W` · `4 B`
* `0x68 R` · `2 B`
* `no answer`, `Incomplete transfer` or `Clock without START` when something
  fails

## How to start

With nothing drawn, the status box explains:

> *No transfer yet. With SCL high, pull SDA low for the START; after that every
> rising edge of SCL reads one bit of SDA.*