> ## Documentation Index
> Fetch the complete documentation index at: https://docs.oryx.mechatronstudio.com/llms.txt
> Use this file to discover all available pages before exploring further.

# CAN

> Standard and extended frames, with the CRC checked and stuff bits.

Every sub-step is one bit. The bus idles **recessive**, and the **SOF** is the
first dominant bit.

## Setting

| Setting            | Options   | Default |
| ------------------ | --------- | ------- |
| **Dominant level** | Low, High | Low     |

> A CAN bus idles recessive. On a transceiver pin that is the high level, so the
> **dominant is low**.

## Frame fields

| Field               | What it is                                                       |
| ------------------- | ---------------------------------------------------------------- |
| **SOF**             | Start of frame: one dominant bit                                 |
| **ID**              | 11-bit identifier. The lower it is, the higher the priority      |
| **SRR**             | Takes the place of RTR in extended frames. Always recessive      |
| **IDE**             | Dominant: standard frame. Recessive: extended frame              |
| **Extended ID**     | The 18 bits that complete the 29-bit identifier                  |
| **RTR**             | Dominant: data frame. Recessive: remote request                  |
| **r1 / r0**         | Reserved bits, sent dominant                                     |
| **DLC**             | How many data bytes follow (0 to 8)                              |
| **Data**            | The payload bytes                                                |
| **CRC**             | 15 check bits over everything before it                          |
| **CRC delimiter**   | One recessive bit                                                |
| **ACK**             | Any node that received the frame correctly pulls it dominant     |
| **ACK delimiter**   | One recessive bit                                                |
| **EOF**             | End of frame: 7 recessive bits                                   |
| **IFS**             | Interframe space: 3 recessive bits                               |
| **Stuff bit**       | Added by the protocol after 5 equal bits; carries no information |
| **Error flag**      | 6 or more dominant bits in a row                                 |
| **Error delimiter** | 8 recessive bits                                                 |

## What is checked

The reader **computes the CRC** and compares it with the drawn one, and checks
the bit stuffing, the delimiters and the framing.

| Label             | What did not add up                                          |
| ----------------- | ------------------------------------------------------------ |
| **Stuff error**   | Missing stuff bit: 6 equal bits in a row                     |
| **Incomplete**    | The frame ends before it is complete                         |
| **CRC error**     | The CRC does not match; the message gives the computed value |
| **No ACK**        | Nobody acknowledged: the ACK slot stayed recessive           |
| **CRC delimiter** | The CRC delimiter must be recessive                          |
| **ACK delimiter** | The ACK delimiter must be recessive                          |
| **EOF error**     | End of frame must be 7 recessive bits                        |
| **SRR dominant**  | In an extended frame the SRR must be recessive               |
| **Reserved bit**  | Reserved bits must be dominant                               |
| **DLC > 8**       | DLC is over 8; 8 data bytes are sent anyway                  |
| **Error flag**    | There is an error flag on the bus                            |

## The summary

Each frame is summed up in one line with the identifier and the essentials:

* `ID 0x1A3` · `DLC 8` · `CRC ✓`
* `ID 0x18FF50E5 ext` for extended ones
* `RTR requests 4 B` for a remote request
* `CRC ✗`, `no ACK`, `Incomplete frame` or `Error flag` when something fails

## How to start

With nothing drawn, the status box explains:

> *No frame on this channel yet. Each sub-step is one bit: the bus idles
> recessive and the SOF is the first dominant bit.*